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| PROTECTION PRODUCTS - RailClamp(R) Description RailClamps are surge rated diode arrays designed to protect high speed data interfaces. The SRDA series has been specifically designed to protect sensitive components which are connected to data and transmission lines from overvoltage caused by electrostatic discharge (ESD), electrical fast transients (EFT), and lightning. The unique design incorporates surge rated, low capacitance steering diodes and a TVS diode in a single package. During transient conditions, the steering diodes direct the transient current to ground via the internal low voltage TVS. The TVS diode clamps the transient voltage to a safe level. The low capacitance array configuration allows the user to protect up to four high-speed data lines. The SRDA05-4 may be used to protect lines operating up to 5 volts while the SRDA12-4 may be used on lines operating up to 12 volts. These devices are in a 8-pin SOIC package. They are available with a SnPb or RoHS/WEEE compliant matte tin lead finish. The high surge capability (Ipp=25A, tp=8/20s) means it can be used in high threat environments in applications such as CO/CPE equipment, telecommunication lines, and video lines. RailClamp(R) Low Capacitance TVS Diode Array Features Transient protection for high-speed data lines to IEC 61000-4-2 (ESD) 15kV (air), 8kV (contact) IEC 61000-4-4 (EFT) 40A (5/50ns) IEC 61000-4-5 (Lightning) 24A (8/20s) Array of surge rated diodes with internal TVS diode Protects four I/O lines Low capacitance (<15pF) for high-speed interfaces Low operating and clamping voltages Solid-state technology SRDA05-4 and SRDA12-4 Mechanical Characteristics JEDEC SOIC-8 package Lead Finish: SnPb or Matte Sn Molding compound flammability rating: UL 94V-0 Marking : Part number, date code, logo Packaging : Tape and Reel per EIA 481 Applications USB Power and Data Line Protection T1/E1 secondary IC Side Protection T3/E3 secondary IC Side Protection HDSL, SDSL secondary IC Side Protection Video Line Protection Microcontroller Input Protection Base stations I2C Bus Protection Circuit Diagram Schematic and PIN Configuration REF1 I/O 1 1 8 REF 2 I/O 1 I/O 2 I/O 3 I/O 4 REF 1 2 7 I/O 4 REF 1 REF2 3 6 I/O 3 I/O 2 4 5 REF 2 S0-8 (Top View) Revision 8/21/07 www.semtech.com 1 SRDA05-4 and SRDA12-4 PROTECTION PRODUCTS Absolute Maximum Rating R ating Peak Pulse Power (tp = 8/20s) Peak Forward Voltage (IF = 1A, tp=8/20s) Lead Soldering Temp erature Op erating Temp erature Storage Temp erature Symbol Pp k VFP TL TJ TSTG Value 500 1.5 260 (10 sec.) -55 to +125 -55 to +150 Units Watts V C C C Electrical Characteristics (T=25oC) SR DA05-4 Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamp ing Voltage Clamp ing Voltage Clamp ing Voltage Peak Pulse Current Junction Cap acitance Symbol VRWM V BR IR VC VC VC IP P Cj It = 1mA VRWM = 5V, T=25C IPP = 1A, tp = 8/20s IPP = 10A, tp = 8/20s IPP = 25A, tp = 8/20s tp = 8/20s Between I/O p ins and Ground VR = 0V, f = 1MHz Between I/O p ins VR = 0V, f = 1MHz 8 6 10 9.8 12 20 25 15 Conditions Minimum Typical Maximum 5 Units V V A V V V A pF 4 pF (c) 2007 Semtech Corp. 2 www.semtech.com SRDA05-4 and SRDA12-4 PROTECTION PRODUCTS Electrical Characteristics (continued) SR DA12-4 Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamp ing Voltage Clamp ing Voltage Clamp ing Voltage Peak Pulse Current Junction Cap acitance Symbol VRWM V BR IR VC VC VC IP P Cj It = 1mA VRWM = 12V, T=25C IPP = 1A, tp = 8/20s IPP = 10A, tp = 8/20s IPP = 20A, tp = 8/20s tp = 8/20s Between I/O p ins and Ground VR = 0V, f = 1MHz Between I/O p ins VR = 0V, f = 1MHz 8 13.3 1 17 20 25 20 15 Conditions Minimum Typical Maximum 12 Units V V A V V V A pF 4 pF (c) 2007 Semtech Corp. 3 www.semtech.com SRDA05-4 and SRDA12-4 PROTECTION PRODUCTS Typical Characteristics Non-Repetitive Peak Pulse Power vs. Pulse Time 10 Peak Pulse Power - Ppk (kW) Power Derating Curve 110 100 % of Rated Power or PP I 90 80 70 60 50 40 30 20 10 1 0.1 0.01 0.1 1 10 Pulse Duration - tp (s) 100 1000 0 0 25 50 75 100 125 150 Ambient Temperature - TA (oC) Pulse Waveform 110 100 90 80 Percent of IPP 70 60 50 40 30 20 10 0 0 5 10 15 T im e (s) 20 25 30 td = I PP /2 e -t W aveform Parameters: tr = 8s td = 20s Clamping Voltage vs. Peak Pulse Current 22 20 Clamping Voltage - VC (V) 18 16 14 12 10 8 6 4 2 0 0 5 10 15 20 25 30 Peak Pulse Current - IPP (A) Waveform Parameters: tr = 8s td = 20s SRDA3.3-4 SRDA05-4 SRDA12-4 Variation of Capacitance vs. Reverse Voltage 1.04 Forward Voltage vs. Forward Current 10 9 Forward Voltage - VF (V) 8 7 6 5 4 3 2 1 0 0 5 10 15 20 25 30 35 Waveform Parameters: tr = 8s td = 20s 40 45 50 1.02 1 Cj (VR) / Cj (VR=0) 0.98 0.96 0.94 0.92 0.9 0.88 0 0.5 1 1.5 2 2.5 3 3.5 Reverse Voltage - VR (V) Forward Current - IF (A) (c) 2007 Semtech Corp. 4 www.semtech.com SRDA05-4 and SRDA12-4 PROTECTION PRODUCTS Applications Information Device Connection Options for Protection of Four High-Speed Lines The SRDA TVS is designed to protect four data lines from transient overvoltages by clamping them to a fixed reference. When the voltage on the protected line exceeds the reference voltage (plus diode VF) the steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. Data lines are connected at pins 1, 4, 6 and 7. The negative reference is connected at pins 5 and 8. These pins should be connected directly to a ground plane on the board for best results. The path length is kept as short as possible to minimize parasitic inductance. The positive reference is connected at pins 2 and 3. The options for connecting the positive reference are as follows: 1. To protect data lines and the power line, connect pins 2 & 3 directly to the positive supply rail (VCC). In this configuration the data lines are referenced to the supply voltage. The internal TVS diode prevents over-voltage on the supply rail. 2. The SRDA can be isolated from the power supply by adding a series resistor between pins 2 and 3 and VCC. A value of 10k is recommended. The internal TVS and steering diodes remain biased, providing the advantage of lower capacitance. 3. In applications where no positive supply reference is available, or complete supply isolation is desired, the internal TVS may be used as the reference. In this case, pins 2 and 3 are not connected. The steering diodes will begin to conduct when the voltage on the protected line exceeds the working voltage of the TVS (plus one diode drop). ESD Protection With RailClamps RailClamps are optimized for ESD protection using the rail-to-rail topology. Along with good board layout, these devices virtually eliminate the disadvantages of using discrete components to implement this topology. Consider the situation shown in Figure 1 where discrete diodes or diode arrays are configured for rail-torail protection on a high speed line. During positive duration ESD events, the top diode will be forward biased when the voltage on the protected line exceeds the reference voltage plus the V drop of the diode. F For negative events, the bottom diode will be biased (c) 2007 Semtech Corp. 5 www.semtech.com Data Line and Power Supply Protection Using Vcc as reference Data Line Protection with Bias and Power Supply Isolation Resistor Data Line Protection Using Internal TVS Diode as Reference SRDA05-4 and SRDA12-4 PROTECTION PRODUCTS Applications Information (continued) when the voltage exceeds the V of the diode. At first F approximation, the clamping voltage due to the characteristics of the protection diodes is given by: V =V +V V = -V C F C CC F PIN Descriptions (for positive duration pulses) (for negative duration pulses) However, for fast rise time transient events, the effects of parasitic inductance must also be considered as shown in Figure 2. Therefore, the actual clamping voltage seen by the protected circuit will be: V = V + V + L di C CC F P ESD /dt (for positive duration pulses) (for negative duration pulses) Figure 1 - "Rail-To-Rail" Protection Topology (First Approximation) V = -V - L di C F G ESD /dt ESD current reaches a peak amplitude of 30A in 1ns for a level 4 ESD contact discharge per IEC 61000-4-2. Therefore, the voltage overshoot due to 1nH of series inductance is: V = L di P ESD /dt = 1X10-9 (30 / 1X10-9) = 30V Example: Consider a V = 5V, a typical V of 30V (at 30A) for the CC F steering diode and a series trace inductance of 10nH. The clamping voltage seen by the protected IC for a positive 8kV (30A) ESD pulse will be: V = 5V + 30V + (10nH X 30V/nH) = 335V C Figure 2 - The Effects of Parasitic Inductance When Using Discrete Components to Implement Rail-To-Rail Protection This does not take into account that the ESD current is directed into the supply rail, potentially damaging any components that are attached to that rail. Also note the high V of the discrete diode. It is not uncommon F for the V of discrete diodes to exceed the damage F threshold of the protected IC. This is due to the relatively small junction area of typical discrete components. It is also possible that the power dissipation capability of the discrete diode will be exceeded, thus destroying the device. The RailClamp is designed to overcome the inherent disadvantages of using discrete signal diodes for ESD suppression. The RailClamp's integrated TVS diode helps to mitigate the effects of parasitic inductance in Figure 3 - Rail-To-Rail Protection Using RailClamp TVS Arrays (c) 2007 Semtech Corp. 6 www.semtech.com SRDA05-4 and SRDA12-4 PROTECTION PRODUCTS Applications Information (continued) the power supply connection. During an ESD event, the current will be directed through the integrated TVS diode to ground. The total clamping voltage seen by the protected IC due to this path will be: V =V C F(RailClamp) +V TVS This is given in the data sheet as the rated clamping voltage of the device. For an SRDA05-4 the typical clamping voltage is <16V at I =30A. The diodes PP internal to the RailClamp are low capacitance, fast switching devices that are rated to handle high transient currents and maintain excellent forward voltage characteristics. Using the RailClamp does not negate the need for good board layout. All other inductive paths must be considered. The connection between the positive supply and the SRDA and from the ground plane to the SRDA must be kept as short as possible. The path between the SRDA and the protected line must also be minimized. The protected lines should be routed directly to the SRDA. Placement of the SRDA on the PC board is also critical for effective ESD protection. The device should be placed as close as possible to the input connector. The reason for this is twofold. First, inductance resists change in current flow. If a significant inductance exists between the connector and the TVS, the ESD current will be directed elsewhere (lower resistance path) in the system. Second, the effects of radiated emissions and transient coupling can cause upset to other areas of the board even if there is no direct path to the connector. By placing the TVS close to the connector it will divert the ESD current immediately and absorb the ESD energy before it can be coupled into nearby traces. (c) 2007 Semtech Corp. 7 www.semtech.com SRDA05-4 and SRDA12-4 PROTECTION PRODUCTS Typical Applications Universal Serial Bus ESD Protection LC01-6 8 5 1 4 SRDA05-4 LC01-6 T1/E1 Interface Protection (c) 2007 Semtech Corp. 8 www.semtech.com SRDA05-4 and SRDA12-4 PROTECTION PRODUCTS Applications Information - Spice Model Pin 3 Pin 1 0.6 nH Pin 8 SRDA05-4 & SRDA12-4 Spice Model SRDA05-4 & SRDA12-4 Spice Parameters Parameter IS BV VJ RS IBV CJO TT M N EG Unit Amp Volt Volt O hm Amp Farad sec --eV D1 (LCRD) 2.092E-11 680 0.62 0.180 1.0 E-3 5.2E-12 2.541E-9 0.058 1.1 1.11 D2 (LCRD) 2.156E-12 240 0.64 0.155 1.0 E-3 6.2E-12 2.541E-.9 0.058 1.1 1.11 SRDA05-4 D3 (T VS) 1.4E-14 6.70 .56 0.56 1.0 E-3 307E-12 2.541E-9 0.247 1.1 1.11 SRDA12-4 D3 (T VS) 1.43E-14 15 .78 0.40 1.0 E-3 71E-12 2.541E-9 0.246 1.1 1.11 (c) 2007 Semtech Corp. 9 www.semtech.com SRDA05-4 and SRDA12-4 PROTECTION PRODUCTS Outline Drawing - SO-8 A e N h 2X E/2 E1 E GAGE PLANE 1 ccc C 2X N/2 TIPS 2 e/2 B D aaa C A2 A SEATING PLANE C bxN bbb A1 C A-B D SIDE VIEW SEE DETAIL DETAIL 0.25 L (L1) H c D h DIM A A1 A2 b c D E1 E e h L L1 N 01 aaa bbb ccc DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX .053 .069 .010 .004 .065 .049 .012 .020 .010 .007 .189 .193 .197 .150 .154 .157 .236 BSC .050 BSC .010 .020 .016 .028 .041 (.041) 8 8 0 .004 .010 .008 1.35 1.75 0.10 0.25 1.25 1.65 0.31 0.51 0.17 0.25 4.80 4.90 5.00 3.80 3.90 4.00 6.00 BSC 1.27 BSC 0.25 0.50 0.40 0.72 1.04 (1.04) 8 0 8 0.10 0.25 0.20 01 A A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-012, VARIATION AA. Land Pattern - SO-8 X DIM (C) G Z C G P X Y Z DIMENSIONS INCHES MILLIMETERS (.205) .118 .050 .024 .087 .291 (5.20) 3.00 1.27 0.60 2.20 7.40 Y P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A, RLP NO. 300A. (c) 2007 Semtech Corp. 10 www.semtech.com SRDA05-4 and SRDA12-4 PROTECTION PRODUCTS Marking Diagram Ordering Information Part Number Lead Finish SnPb Matte Sn SnPb Matte Sn Qty per Reel 500 500 500 500 R eel Size 7 Inch 7 Inch 7 Inch 7 Inch SC YYWW SRDA05-4 PHIL SC YYWW SRDA12-4 PHIL SRDA05-4.TB SRDA05-4.TBT SRDA12-4.TB Note: YYWW = Date Code SRDA12-4.TBT Note: Lead-free devices are RoHS/WEEE Compliant Tape and Reel Specification Pin 1 Location User Direction of feed Device Orientation in Tape A0 6.50 +/-0.20 mm B0 5.40 +/-0.20 mm K0 2.00 +/-0.10 mm Tape Width B, (Max) D D1 E F K (MAX) P P0 P2 T(MAX) W 12 mm 8.2 mm 1.5 + 0.1 mm - 0.0 mm 1.5 mm 1.750.10 mm 5.50.05 mm 4.5 mm 4.00.1 mm 4.00.1 mm 2.00.05 mm 0.4 mm 12.0 mm 0.3 Contact Information Semtech Corporation Protection Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 (c) 2007 Semtech Corp. 11 www.semtech.com |
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